In electronic appliances such as an information processing device and the like, a NAND flash memory and an AND flash memory have been recently used as a nonvolatile semiconductor storage device other than a main memory.
FIG. 1 illustrates a configuration of a conventional NAND flash memory. This NAND flash memory includes a logic control circuit 101, a control circuit 102, a column buffer 103, a column decoder 104, a row decoder 105, a memory cell array 106, a data register 107, a status register 108, a command register 109, an I/O control circuit 110, and an address register 111.
Various types of commands, an address and write data are input to the I/O control circuit 110 via an 8-bit interface of I/O 0-7, and data read from the memory cell array 106 is output from the I/O control circuit 110 via the I/O 0-7. An input address is transferred to the column buffer 103 and the row decoder 105 via the address register 111, and an input command is transferred to the control circuit 102 via the command register 109. Input write data is transferred to the data register 107.
The column buffer 103 holds a column address, and the column decoder 104 decodes the column address. The row decoder 105 decodes a row address. The data register 107 holds data read from a decoded address, and also holds data written to a decoded address.
Control signals such as a chip enable signal /CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal /WE, a read enable signal /RE, a write protect signal /WP and the like are input to the logic control circuit 101 from outside. The logic control circuit 101 and the control circuit 102 control various types of operations such as a read from the flash memory, a write to the flash memory, an erasure of the flash memory, verification of the flash memory, and the like on the basis of an input control signal.
On the basis of a command and a control signal, the control circuit 102 controls operations of the column decoder 104 and the row decoder 105, and also controls erasure of the memory cell array 106. Moreover, the control circuit 102 outputs a ready/busy signal RD/BY indicating an operational state to outside, and stores, in the status register 108, information indicating whether or not a write/erasure has been properly terminated. This information is output via the I/O control circuit 110 to outside.
In such a flash memory, it is necessary that a block where a bad bit exists in a memory cell is defined as a bad block and the block is not used to hold data in order to implement a large capacity and a low price. By defining a bad block, the flash memory as a product is enabled to be shipped without being regarded as a defective product.
Methods for identifying a bad block are diverse. Normally, manufacturers mark a bad block by writing data other than logic “1” to a corresponding block, and ship a flash memory. Accordingly, data in all areas or data at a predetermined address is once read to detect a bad block.
FIG. 2 is a flowchart illustrating a bad block generation process executed by a conventional test device. The test device initially sets a block number to “0” (step 201), and checks whether or not a read operation is properly performed from the block (step 202). If the read operation is properly performed as a result of the check, the test device checks whether or not the block number is the last number (step 203). If the block number is not the last number, the test device increments the block number by 1 (step 204), and repeats the processes in and after step 202.
If the read operation is not properly performed as a result of the check in step 202, the test device writes, to the block, a management code indicating a bad block (step 205), and repeats the processes in and after step 203. When the block number reaches the last number, the test device terminates the process.
The following Patent Document 1 relates to a semiconductor storage device having a circuit configuration where a high voltage is not applied to a bad block in test mode. Patent Document 2 relates to a method for examining a memory card without destroying initial bad information stored in a flash memory. Patent Document 3 relates to a method for reducing a test time of a nonvolatile semiconductor memory.
Patent Document 1: Japanese Laid-open Patent Publication No. H8-106796
Patent Document 2: Japanese Laid-open Patent Publication No. H7-306922
Patent Document 3: Japanese Laid-open Patent Publication No. 2001-273798